Semiconductor wafer-map defect classification & fab yield analytics

A modern fab produces thousands of wafers per week, each with hundreds to thousands of dies and many inline inspection and review steps. Yield engineers must decide which spatial patterns and defect types matter and which tool or process step caused them. Computer vision classifies defect review images (automatic defect classification, ADC) and wafer-map patterns, and joins the signatures to equipment genealogy to shorten the path from "yield dropped" to "chamber X needs maintenance". The result is faster excursion containment and less manual image review.

Problem & value

• Today: inspection tools flag candidate defects; a sample is revisited on an SEM review tool and classified by operators or rule-based ADC. Wafer-map patterns are eyeballed by yield engineers or caught by rule-based spatial filters. Root-cause work is a manual hunt through lot/tool histories in spreadsheets and yield-management software.
• AI value: consistent, fast classification of review images and wafer-map signatures; fewer unclassified or mislabelled defects; automatic commonality analysis (which tool/chamber/recipe step is over-represented among bad wafers); earlier excursion detection; less operator time on routine classification. Vendors report ADC accuracy and purity improvements, but figures are vendor- and process-specific; measure on your own data rather than quoting generic numbers [2][3].
• Strategic context: the EU Chips Act aims to strengthen European semiconductor capacity; yield and ramp speed are central to the economics of new European fabs and pilot lines [4].

Variants

• Wafer-map pattern classification (sort/probe): classify whole-wafer bin maps into pattern families (centre, donut, edge-ring, edge-local, local cluster, scratch, random, near-full), including mixed-pattern wafers.
• ADC on SEM/optical review images: per-defect classification, often with "unknown/novel" handling.
• Inline inspection nuisance filtering: suppress false calls from brightfield/darkfield tools.
• Yield and commonality analytics: link signatures to tools, chambers, steps and parametric data.
• Back-end / OSAT: substrate, bump, die-attach and package-level visual defects plus final-test maps.
• Compound, power and MEMS fabs: smaller volumes, fewer labelled examples; more few-shot / anomaly methods.

How it works

1. inspection tools + SEM review + probe/sort + e-test + equipment genealogy (MES/EDA)
2. data harmonisation (lot/wafer/die keys, coordinates, timestamps)
3. defect-image ADC (CNN/ViT classifier, "unknown" class, active learning queue)
4. wafer-map pattern classifier / segmentation of spatial signature
5. commonality & root-cause analysis (tool/chamber/step vs. signature; tabular ML, SHAP)
6. excursion alert + lot hold recommendation
7. yield engineer review
8. feedback: confirmed labels retrain models; fix logged in yield-management system

• ADC: supervised CNN or vision-transformer classifiers on cropped review images, with a reject/unknown option; low-confidence images go to an operator queue (human-in-the-loop). Labels come from the existing defect taxonomy.
• Wafer maps: treated as small images (die grid) or as point sets; CNNs, ViTs, autoencoders and self-supervised features are used, plus synthetic augmentation for rare classes.
• Root cause: tabular ML and statistical commonality tests across genealogy; graph methods help when wafers pass through shared tool sets. Findings are hypotheses; engineers verify physically.
• Human-in-the-loop: yield engineers confirm new defect classes, approve lot holds and tool-down actions.

Data preparation

Data quality decides success here; expect most of the effort in this step.

• Data and location: wafer maps (STDF, KLARF, CSV) sit in the MES/yield management system, inspection tool servers and file shares; defect images and review results sit in separate image stores; lot, recipe and equipment history lives in the MES or ERP.
• Typical gaps: inconsistent formats between tool vendors, missing or contradictory defect labels, few examples of rare patterns, unlinked maps and process context, labels that only exist in engineers' heads or e-mails, and strict access rights from customers or foundries.
• Preparation steps: inventory sources, convert maps into a uniform array format, link each map to lot, tool and process step, agree a defect-pattern scheme (scratch, ring, edge, cluster), harvest labels from existing review records, have two engineers relabel a test sample, and build a held-out evaluation set. Add augmentation or synthetic examples for rare classes.
• Tools: Python with pandas and open wafer-map libraries, a labelling tool such as Label Studio, a feature or image store.
• Share of effort: high, typically 50-70 percent.

Useful building blocks: PREP-005, PREP-019, PREP-020, PREP-018 and PREP-024.

Implementation paths

Which path for whom

• Enterprise (fabs, semiconductor and electronics manufacturers): Path C, because wafer maps and defect images are core process data and trade secrets, volumes make seat or API costs high, and a self-hosted model on HW2 can run next to the inspection tools.
• Developer (tool vendors, integrators, yield-software builders): Path C, because open-weight vision models and own training pipelines are the product basis and avoid lock-in; Path D is the natural extension once labelled data exists.

Path A — Buy

• Inspection/review OEMs: KLA (inspection, review and ADC software; Klarity/Surfscan ecosystem), Applied Materials (SEMVision review with ADC, Enlight), Hitachi High-Tech, ASML (YieldStar optical metrology; NL, EU), Lasertec (mask inspection) and Zeiss (EU) for specific applications [2][3][6].
• Yield/data platforms: PDF Solutions Exensio, Synopsys Yield Explorer, Siemens EDA (Tessent Diagnosis/YieldInsight), Onto Innovation (Discover), Galaxy Semiconductor; European: Siemens EDA, ASML, Zeiss, Semilab (HU), Camtek/Nova (IL, widely used in EU fabs) [3].
• When right: production fabs with commercial inspection fleets; the ADC engine is usually tied to the tool vendor's data format.

Path B — Build on cloud APIs

• Use cloud ML platforms (Azure ML, Vertex AI, Amazon SageMaker, EU regions) for training and batch scoring of images and maps; ingest through the fab data lake. Frontier VLMs (Claude, Gemini, GPT, Mistral) are useful as labelling assistants or for describing novel defects from review images, but are not accurate or fast enough for in-line ADC and should never receive unreleased process images without an NDA/contract: fab images are highly confidential IP.

Path C — Self-host (open source)

• Models/tools: PyTorch with timm backbones; DINOv2 self-supervised features for few-shot and novel-class discovery; Anomalib (OpenVINO) for anomaly detection; Ultralytics/MMDetection for detection of defects in large images; Label Studio or CVAT for labelling; MLflow for tracking; ONNX Runtime / TensorRT for edge inference at the tool [5][7][8].
• Public data: WM-811K (about 811k real wafer maps, ~20% labelled with 9 classes) and the synthetic MixedWM38 are the standard benchmarks; real fab data is far more varied [1].
• Hardware: HW2 (one 24–32 GB GPU) suffices for training modest classifiers and inference; HW1 edge boxes at the review tool for latency.

Path D — Custom training

Most common in practice for fabs with proprietary processes: train or fine-tune on in-house labelled review images and wafer maps. Needs thousands of labelled defects per class group, a stable taxonomy, and handling of strong class imbalance. Use active learning to focus operator labelling, and retrain per technology node or layer when appearance changes.

State of the art (2026)

• Wafer-map classification on WM-811K is saturated by CNN/ViT models (papers report very high accuracy), but this overstates difficulty: the dataset is small-image, class-imbalanced and labelled by few annotators. Real challenges are mixed patterns, rare classes and drift.
• Self-supervised and foundation-style backbones reduce labelling needs; few-shot and open-set methods flag novel signatures instead of forcing a known class.
• Anomaly detection (PatchCore-style, flow-based) supports defect detection with few defect examples.
• Synthetic data (generative augmentation of rare patterns) is used to balance classes; validate on real wafers.
• Fab-wide AI links ADC, FDC and metrology for root-cause suggestions; LLM copilots over yield-management data are appearing as natural-language interfaces.
• Limits: domain shift across nodes, tools and layers; confidentiality limits data sharing and public benchmarks; label noise in historical classifications; correlation in commonality analysis is not causation; classifiers can be confidently wrong on novel defects.

Shared resources & combinations

• Same CV stack as VIS-001 (line inspection), VIS-053 (NDT evaluation) and VIS-057 (additive manufacturing in-situ monitoring): labelling tools, edge inference runtimes, drift monitoring.
• Upstream/downstream: PRED-014 (virtual metrology and process quality prediction from sensor data) and ANOM-005 (industrial process anomaly detection) share the genealogy and FDC data and combine naturally with wafer-map signatures for earlier excursion detection.
• Data pipelines: a shared fab data lake keyed by lot/wafer/die is the common prerequisite.

Effort, cost & KPIs

• Path A: months for qualification and integration; licence plus tool-bundle cost.
• Path B/C: 6–12 months for a production-grade ADC with MES and yield-system integration.
• Path D: dominated by labelling, taxonomy governance and model lifecycle management.
• KPIs: classification accuracy and purity per class, unknown-rate, operator hours per review lot, time-to-detect and time-to-contain an excursion, yield learning rate, scrap and re-inspection rate, false-alarm rate on holds.

People & change

Begin with management and the yield or process-engineering lead, who own the goal, and the data owners of MES and inspection systems, whose cooperation sets the pace. Engineers and operators who review defects are the end users and the source of labels: involve them from day one, since their corrections improve the model. IT and IT security cover integration, network zones and protection of process data; suppliers and customers may restrict how data is used, so check contracts with legal.

Works council: depends. Wafer-map classification does not monitor people, but operator review logs, decision times and override rates can show behaviour, so under §87(1) no. 6 BetrVG co-determination is likely if such data is recorded. Inform the works council early under §90(1) no. 3 anyway, because work processes change. Data protection: mostly no personal data, but user logs are; the DPO needs a short check.

AI literacy: support engineers with training on model confidence, drift and failure on unseen patterns (AI Act Art. 4). Pilot on one product line with the model running in shadow mode next to manual classification, and define a go/no-go. Typical concern: deskilling and blame for misses; address it by keeping engineers in the decision loop, with the model proposing and humans confirming low-confidence cases.

See GUIDE-009, GUIDE-011, GUIDE-008 and for the works council GUIDE-004.

Risks, regulation & compliance

• EU AI Act: minimal risk; this is an industrial quality system without individuals as subject. Not a safety component under Annex I/III. AI literacy duty (Art. 4) applies. No Art. 5 issue.
• GDPR: generally no personal data (wafer images, tool IDs); operator IDs in logs are the only personal data; apply pseudonymisation where possible.
• Trade secrets and export control: process images and yield data are core IP; EU Trade Secrets Directive, customer NDAs, and export controls (EU Dual-Use Regulation 2021/821) can affect data sharing and cloud use. Prefer on-premises or sovereign EU cloud.
• Sector rules: automotive customers require traceability and containment (IATF 16949, AEC-Q standards); SEMI standards govern equipment data interfaces (SECS/GEM, EDA/Interface A).
• Mitigations: keep humans in the loop for novel classes and holds, monitor drift, log model versions per lot decision, and run shadow mode before automating dispositions.

Getting started

1. Inventory data: wafer-map formats (STDF), review image archives, defect taxonomy, genealogy sources.
2. Benchmark the current ADC on a held-out set of your own labelled images and wafer maps.
3. Train a baseline wafer-map classifier and an image classifier with an explicit "unknown" class.
4. Run in shadow mode next to engineers for one or two product families; track disagreements.
5. Add commonality analysis on top of confirmed signatures; measure time-to-root-cause.

Sources

1. Wu et al., "Wafer Map Failure Pattern Recognition and Similarity Ranking for Large-Scale Data Sets" (WM-811K), IEEE TSM 2015; dataset mirror at https://www.kaggle.com/datasets/qingyi/wm811k-wafer-map
2. KLA — Inspection and process control products — https://www.kla.com/products
3. PDF Solutions — Exensio analytics platform — https://www.pdf.com/products/exensio-analytics-platform/overview/
4. Regulation (EU) 2023/1781 (European Chips Act) — https://eur-lex.europa.eu/eli/reg/2023/1781/oj
5. Anomalib (OpenVINO) — https://github.com/open-edge-platform/anomalib
6. Applied Materials — Defect inspection and review — https://www.appliedmaterials.com/us/en/semiconductor/products/process-diagnostics-and-control.html
7. DINOv2 (Meta) — https://github.com/facebookresearch/dinov2
8. SEMI standards (SECS/GEM, EDA) — https://www.semi.org/en/standards
9. Regulation (EU) 2024/1689 (AI Act) — https://eur-lex.europa.eu/eli/reg/2024/1689/oj